For porous low-k dielectric materials, traditional dual damascene patterning processes normally suffer surface roughness issues which will induce metallization issues. The major contribution to this surface roughness derives from the liner removal process (LRM). A trade-off between a sufficient LRM etch rate to open the stop layer and the dual damascene porous low-k surface roughness is very difficult to resolve.
U.S. Pat. No. 6,350,681 B1 to Chen et al. describes a dual damascene comprising an etch via and an etch trench.
U.S. Pat. No. 6,291,887 B1 to Wang et al. describes a dual damascene with low-k layers comprising an etch via and an etch trench with a nitride middle etch stop layer.
U.S. Pat. No. 6,287,955 B1 to Wang et al. describes a dual damascene with multiple low-k intermetal dielectric layers comprising an etch via and an etch trench.
U.S. Pat. No. 6,300,235 B1 to Feldner et al. describes a dual damascene with low-k layers comprising an etch via and an etch trench with sacrificial flowable oxide.